1.Field of the Invention
The present invention relates overall to the technical field of direct current to direct current (DC-DC) power supplies, and more particularly to a DC-DC Buck circuit.
2.Description of the Prior Art
DC-DC conversion technology is currently widely used in fields such as household electrical appliances, digital products, and aeronautics and astronautics, with an ever increasing number of applications requiring the use of DC-DC power supply modules. A DC-DC Buck circuit is a circuit which makes the output voltage lower than the input voltage by switching or linear step-down, with both the input and the output being DC. There are two types of DC-DC Buck circuit, non-synchronous (asynchronous) and synchronous.
FIG. 1 shows a diagram of a typical asynchronous DC-DC Buck circuit, which includes a switch S, inductor L, flyback diode VD, load Rload and capacitor C. When the switch S is conducting, the input voltage supplies power to the load Rload via the inductance L, at the same time charging the capacitor C; during this process, the capacitor C and inductor L store energy. When the switch S is opened, the inductor L, load Rload and flyback diode VD form a loop, and the energy stored in the inductor L continues to supply power to the load Rload; when the output voltage is about to fall, the energy in the capacitor C also discharges into the load Rload, to maintain a constant output voltage.
FIG. 2 shows a conventional synchronous DC-DC Buck circuit, in which an upper tube switch G1 is used for establishing or stopping conduction between a DC input terminal 6 and an inductor L, and a lower tube switch G2 is used for flyback current when the inductor L and DC input terminal 6 are isolated from each other. The Buck circuit has a first type of PWM control chip 10, for example an LTC3855 produced by Linear, or a TPS40140 produced by Texas Instruments, wherein only some of the pins are shown. The first type of PWM control chip 10 acts in cooperation with 5 external sub-circuits (indicated by the dotted line boxes in FIG. 2) to drive the opening and closing of discrete external switches. The chip comprises an upper tube driver HG and a lower tube driver LG, wherein the upper tube driver HG is used to switch the upper tube switch G1 on or off, and the lower tube driver LG is used to switch the lower tube switch G2 on or off; there is a 180-degree phase difference between the upper tube driver HG and the lower tube driver LG. The upper tube driver HG and lower tube driver LG of the first type of PWM control chip 10 are used to produce a PWM control signal; drive circuits in the first sub-circuit 1 and second sub-circuit 2 in FIG. 2 drive the upper tube switch G1 and the lower tube switch G2 alternately according to the PWM control signal of the first type of PWM control chip 10. As shown in FIG. 2, and as is well known to those skilled in the art, in order to enable the upper tube driver to drive the upper tube switch in a floating manner, the first type of PWM control chip 10 must be provided with a BOOT pin for a bootstrap power supply terminal and an SW pin for an upper tube drive signal loop. The Boot and SW pins of the upper tube driver HG cooperate with the drive circuit of the fifth sub-circuit 5, and are used to supply power to the drive circuit of the upper tube switch G1, so that when the gate voltage of the upper tube switch G1 is higher than the source voltage and greater than the switch-on voltage VGS(TH), the upper tube switch G1 can conduct well. The circuit also comprises noise reduction circuits of third and fourth sub-circuits 3 and 4, used to suppress switching noise in the upper tube switch G1 and lower tube switch G2. The Buck circuit also has a sampling resistance 9. The first type of PWM control chip 10 also has an FB pin for monitoring output voltage, and CSP/CSN (positive current sampling/negative current sampling) pins connected to the sampling resistance 9, for adjusting the output voltage of the Buck circuit according to feedback voltage and feedback current. The CSP pin is connected to the positive pole of the sampling resistance 9, while the CSN pin is connected to the negative pole of the sampling resistance 9, for the purpose of monitoring the voltage across the sampling resistance 9; moreover, feedback current can be obtained on the basis of the sampling resistance 9 and the potential difference across it. The first type of PWM control chip 10 imposes no restrictions in terms of level on the CSP, so the latter can receive a relatively wide range of voltages; for example, the CSP of the first type of PWM control chip can receive a voltage of 5.5 V or even higher. Although this conventional synchronous DC-DC Buck circuit can produce a relatively high output voltage, the PWM control chip 10 in the circuit is only used for compatibility with the external discrete switch (e.g. MOSFET) circuits, i.e. the above-mentioned 5 external sub-circuits must be configured, with the result that the volume of the product is quite large, and positioning of circuits is inconvenient.
To solve this problem, a DrMOS chip design has been proposed in the prior art, in which the conventional two discrete sets of switches and drive circuits for supplying power to switches are integrated in a single chip by a more advanced process, so that the system is more stable and energy-saving in operation. FIG. 3 shows a common DC-DC Buck circuit, comprising a DrMOS chip 20 consisting of an upper tube switch C1, a lower tube switch G2 and a drive circuit, as well as a second type of PWM control chip 11 (e.g. NCP5314, produced by ON Semiconductor, or L6716, produced by ST Microelectronics) for supplying a logic level to the DrMOS chip. The second type of PWM control chip 11 referred to here is a chip specially intended to cooperate with the DrMOS chip 20, and is different from the first type of PWM control chip 10 mentioned above; the first type can drive switches, whereas the second type lacks this function. The drive circuit in the DrMOS chip 20 is used for driving the upper tube switch G1 and lower tube switch G2 alternately according to the logic level supplied by the second type of PWM control chip 11. The advantage of such a DC-DC Buck circuit is that it can for example integrate two MOSFET drivers, an upper tube MOSFET and a lower tube MOSFET in a 40-pin QFN package measuring 6 mm by 6 mm or 8 mm by 8 mm, so it is more compact and efficient than the conventional circuit shown in FIG. 2. However, since the second type of PWM control chip 11 used in conjunction with the DrMOS chip 20 places level restrictions on the CSP pin, with the CSP of the second type of PWM control chip perhaps for example being at a voltage of less than 5.5 V, it is generally impossible to supply a higher output voltage; when the input is 12 V, the output voltage supplied is less than 5.5 V.